ATA8741-PXQW【PDF 98/238 页】MCU W/TRANSMITTER ASK/FSK 24QFN

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Sheet目录52

94页 95页 96页 97页 [98页]99页 100页 101页 102页

9140CINDCO02/10

ATA8741

one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is

not available for the OC0B pin (See Table 20-4 on page 101). The actual OC0x value will only

be visible on the port pin if the data direction for the port pin is set as output. The PWM wave-

form is generated by clearing (or setting) the OC0x Register at the Compare Match between

OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at

Compare Match between OCR0x and TCNT0 when the counter decrements. The PWM fre-

quency for the output when using phase correct PWM can be calculated by the following

equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the

output will be continuously low and if set equal to MAX the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of period 2 in Figure 20-7 on page 97 OCn has a transition from high to low

even though there is no Compare Match. The point of this transition is to guaratee symmetry

around BOTTOM. There are two cases that give a transition without Compare Match.

" OCR0A changes its value from MAX, like in Figure 20-7 on page 97. When the OCR0A value

is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To

ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an

up-counting Compare Match.

" The timer starts counting from a value higher than the one in OCR0A, and for that reason

misses the Compare Match and hence the OCn change that would have happened on the way

up.

20.8 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk

) is therefore shown as a

clock enable signal in the following figures. The figures include information on when Interrupt

Flags are set. Figure 20-8 on page 98 contains timing data for basic Timer/Counter operation.

The figure shows the count sequence close to the MAX value in all modes other than phase cor-

rect PWM mode.

Figure 20-8. Timer/Counter Timing Diagram, no Prescaling

Figure 20-9 on page 99 shows the same timing data, but with the prescaler enabled.

OCnxPCPWM

clk_I/O

N 510

?/DIV>

-------------------- -

clk

I/O

/1)

TOVn

clk

I/O

CNTn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

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